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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/14/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY fsm_packetgen_8_2 IS
	PORT (	clock_lfsr		: IN  STD_LOGIC;	-- PosEdge Clock used	
			reset_crc		: OUT STD_LOGIC;	-- Resets CRC (inits)
			enable_crc		: OUT STD_LOGIC;	-- Enable CRC generation
			init_crc		: OUT STD_LOGIC
			);
END fsm_packetgen_8_2;

ARCHITECTURE behav OF fsm_packetgen_8_2 IS
BEGIN
	PROCESS (clock_lfsr)
	BEGIN
		IF (clock_lfsr'EVENT AND clock_lfsr='0') THEN -- @ NegEdge Clock
			enable_crc <= '1';
			reset_crc <= '0';	
			init_crc <= '1';		
		END IF;
	END PROCESS;
END behav;
